As technology evolves into era of sub-micron, there is a desire to integrate various two-terminal device elements such as but not limited to memory elements with high speed logic circuit elements into a single chip or an integrated circuit (IC) to form an embedded memory. An example of the two-terminal device element is a magnetic random access memory (MRAM) element which gains popularity in recent years. MRAM, for example, includes magnetic tunnel junction (MTJ) stack layers sandwiched between top and bottom electrodes or terminals. The MTJ stack layers are generally connected to interconnects in the interlevel dielectric (ILD) layer. To achieve a desired cell size, there is a desire to embed MTJ element in between adjacent metal levels with tight pitch, such as defined at 1× design rule. It is also desirable to embed MTJ element in 1× layers since 1× layers include common components for all offered back-end-of-line (BEOL) stacks, which include contacts. This is not the case for the other metal levels with relaxed pitch, such as 2×, 4× or 6X×. For example, relaxed pitch metal levels do not cover all offered BEOL stacks. Typically, relaxed pitch metal levels only cover one or a few of the available BEOL stack options.
However, it is difficult to integrate the two-terminal device element with logic circuit element in layers having tight pitch (e.g., defined at 1× design rule) since each of these elements has different requirements. For example, the total height of the MTJ stack and top/bottom electrode may not be compatible with the height of the via contact of the logic circuit which is generally shallower than the MTJ element for metal layers with tight pitch. Thus, during integration, the reliabilities of the two-terminal elements such as memory elements may degrade due to the process limitation and tight pitch between layers which cause electrical shorts between metal line and conductive layers of the two-terminal elements.
Accordingly, it is desirable that the process of manufacturing two-terminal device element to be highly compatible with shallow via interconnects in logic processing and it is also desirable to integrate the two-terminal device elements with logic devices into a single chip or an IC in a reliable, simplified and cost effective way.